Theoretical Aspects of the Optical Transpose Interconnecting System Architecture

An attractive way of implementing efficient local interconnection networks is to use the Optical Transpose Interconnecting System (OTIS) architecture proposed in [8]. This system allows to optically interconnect some set of processors in a Free Space of Optical Interconnections (FSOI). Briefly, it consists of two lenslet arrays allowing a large number of optical interconnections from a set of transmitters to a set of receivers. Note that the OTIS architecture is indeed a three dimension (3D) one but it can always be modelized in a 2D-space. Two approaches exist, in the first one (All-Optical) the OTIS architecture provides all the interconnections of the network in one-hop, while in the second (Hybrid), some electronic connections are necessary and moreover some connections are directly implemented but may require several hops. The hybrid approach has been motivated by the results of [5], where it was shown that as soon as an electronic wire is more than 1 cm long, it has more power consumption than its optical conterpart which connects an optical transmitter to an optical receiver through a FSOI. Consequently, the OTIS architecture was used in [9] to realize parts of interconnection networks such as hypercubes, 4-D meshes, mesh-of-trees and butterflies. The All-Optical approach is enhanced by the opportunity, offered with the OTIS architecture, to easily build a real one-to-one symmetric complete digraph with loops (K∗ n). In fact, using this architecture, it is practically possible to connect 64 processors in a complete graph [7], each processor having 64 transceivers (corresponding to the 64 arcs of one vertex). It has also been shown in [4] how to realize the single-hop multiOPS POPS network [2], and the multi-hop multi-OPS stack-Kautz network [3] with the OTIS architecture. In this work, we focus on All-Optical networks. The number of transceivers per processor is technologically limited (the number of transceivers per cm cannot exceed 64 at the moment). Also, whereas a network having the topology of a complete graph with 64 processors is actually feasible and is an important advance for network design, it is not enough as one can wish layouts for large networks having hence bounded degree (d 64). Moreover, a low number of transceivers per processor means a reduced price per processor. Consequently, it is important to study the set of network topologies for which it exists an efficient layout with the OTIS architecture and to find which “good” networks admit such a layout, we will call it an OTIS2D (OTIS3D). So we will first try to provide ways of determining if a given general network admits an OTIS layout or not. Then we will study particular case of regular and symmetric networks. Finally we will show that classical topologies like de Bruijn, Kautz and complete digraphs admit an OTIS2D-layout. At the end, the results obtained for the OTIS2D model are applied to the OTIS3D case. †Project SLOOP – CNRS-I3S-INRIA – BP 93 – F-06902 Sophia-Antipolis – France. ‡Corresponding author. E-mail: [email protected].